View MC44CC374T1A_4678788.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Freescale Semiconductor
Document Number: MC44CC373 Rev 3.2, 04/2009
CMOS Audio/Video RF Modulators
The MC44CC373 / MC44CC374 CMOS family of RF modulators is the latest generation of the legacy MC44BS373/4 family of devices. The MC44CC373/MC44CC374 RF modulators are designed for use in VCRs, set-top boxes, and similar devices.They support multiple standards, and can be programmed to support PAL, SECAM, or NTSC formats. The devices are programmed by a high-speed I2C Bus. A programmable, internal PLL, with on-chip LC tank covers the full UHF range. The modulators incorporate a programmable, on-chip, sound subcarrier oscillator that covers all broadcast standards. No external tank circuit components are required, reducing PCB complexity and the need for external adjustments. The PLL obtains its reference from a low cost 4 MHz crystal oscillator. The devices are available in a 16-pin SOIC, Pb-free package. These parts are functionally equivalent to the MC44BS373/4 series, but are not direct drop-in replacements. All devices now include the AUXIN found previously only on the 20-pin package option of the MC44BS373. This is a direct input for a modulated subcarrier and is useful in BTSC or NICAM stereo sound or other subcarrier applications. The MC44CC373CASEF has a secondary I2C address for applications using two modulators on one I2C Bus.
MC44CC373CA MC44CC373CAS MC44CC374CA MC44CC374T1A
CMOS AUDIO/VIDEO RF MODULATORS
EF SUFFIX SOIC-16 PACKAGE CASE 751B-05
Features * * * * * * * Multi-TV standard support: NTSC, PAL, SECAM (B/G, I, D/K, L, M/N). UHF operation (460MHz to 880MHz) Programmable UHF oscillator and sound subcarrier oscillator. On-chip tank circuits. No external varicaps inductors or tuned components required. Program control via 800 kHz high-speed I2C-bus. Programmable Sound reference frequency (31.25 kHz or 62.5 kHz) Direct sound modulator input (FM and AM). * * * * * * * Auxiliary input bypasses AM/FM modulators for NICAM or BTSC applications. Video modulation depth (96% typ. in system L and 85% typ. in the other standards) Programmable Peak White Clip levels On-chip video test pattern generator with sound test signal (1 kHz) Low-power standby mode Output inhibit during PLL Lock-up at power-ON Logical output port controlled by I2C-bus
ORDERING INFORMATION
Orderable Part Number(1) Replaces Part Number MC44BS373CAD MC44CC373CAEF, R2 MC44CC373CASEF, R2 MC44CC374CAEF, R2 MC44BS373CAEF MC44BS373CAFC MC44BS373CAFC MC44BS374CAD MC44BS374CAEF MC44BS374T1D MC44CC374T1AEF, R2 MC44BS374T1EF MC44BS374T1AD MC44BS374T1AEF 591.25 591.25 871.25 871.25 89 89 89 89 0xCE 0xCA 0xCA 0xCA Yes Yes Yes Yes Yes No No No Yes Yes Yes Yes 591.25 89 0xCA Yes Yes Yes Default Frequency (MHz) RFOUT(2) (dBV) I2 C Write Address PAL or NTSC Capability SECAM (system L) Capability AUXIN
1. All orderable parts are in a 16-pin SOIC, with temperature range of 0C to +70C ambient. For tape and reel, add the R2 suffix. 2. Refer to application note to obtain 82 dBV or other RF levels.
This document contains certain information on a new product. Specifications and information herein are subject to change without notice.
(c) Freescale Semiconductor, Inc., 2008, 2009. All rights reserved.
PIN DESCRIPTIONS
16-Pin SOIC Package
SDA GND LOP XTAL PREEM AUDIOIN SPLFLT VIDEOIN
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
SCL AUXIN PLLFLT No Connect VCC RFOUT GND VCC
Figure 1. Pin Connections
Table 1. SO16 Package Pin Descriptions Pin Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Pin Name
SDA GND LOP XTAL PREEMP AUDIOIN SPLFLT VIDEOIN VCC GND RFOUT VCC NC PLLFLT AUXIN SCL I2C data Ground
Description
Comments
Bidirectional serial data I/O port for setting configuration. Compatible with 0-5 V and 0-3.3 V I2C-bus.
Logical output port controlled by I2C bus Crystal Pre-emphasis capacitor Audio input Sound PLL loop filter Video input Supply voltage Ground TV output signal Supply voltage No Connection RF PLL loop filter Auxiliary Input I2C clock
Open collector output. Controlled by a single bit in the control register. 4 MHz crystal.
> 20 k input impedance.
1 Volt peak-to-peak baseband video input 3.3 volt power input.
A 75 composite video output signal 3.3 Volt power input. Do not make any connection to this pin.
Subcarrier input for stereo and NICAM applications Serial control port data clock. Compatible with 0-5 V and 0-3.3 V I2C bus.
MC44CC373 2 Digital Home Freescale Semiconductor
FUNCTIONAL OVERVIEW
Figure 2 shows a simplified block diagram of the MC44CC373CA and MC44CC374CA modulators. There are three main sections: 1. 2. 3. A high speed I2C-compatible bus section for control and programming. A PLL section to synthesize the UHF output channel frequency. A modulator section, which accepts audio and video inputs and modulates the RF carrier An on-chip simple video test pattern generator with an audio test signal is included, but is not shown in the block diagram. The MC44CC373/4CA operates as a multi-standard modulator and can handle the following systems using the same external circuit components: B/G, I, D/K, L, M/N. The different orderable part numbers provide: a choice in the pre-programmed power-up default channel frequency, the output power level and a pre-programmed secondary I2C address.
VIDEOIN
8 Peak White Clip Video Modulator L/BG
Internal Control Bus
SPLLFLT
7
VCC
Clamp
12
MODULATOR SECTION
Sound Oscillator and FM Modulator LPF ALC 10 GND 6 Audio Amplifier 5
31.25/62.5 kHz Sound PFD L/BG Program Divider
AUDIOIN PREEM VCC
RFOUT
11
9
LOP
3 RF Sound Modulator
FM L/BG AM AM Modulator 15 AUXIN VHF Dividers
BUS SECTION SCL SDA
16 1 High Speed I2C Bus Receiver
VCO and PLL SECTION
UHF OSC (2 x Fo)
Ref Divider Phase /128 Comp. 31.25 kHz
/2
Prescaler /8 Program Divider
XO Prescaler /1, 2 or 4
13
NO CONNECT
/N11:N0
2
XCO
14
4
GND
PLLFLT
XTAL (4 MHz)
Figure 2. MC44CC373/374 Simplified Block Diagram
MC44CC373 Digital Home Freescale Semiconductor 3
MODES OF OPERATION AND FUNCTIONAL DESCRIPTION
POWER ON SETTINGS At power-on, the modulators are configured with pre-programmed default settings as listed in Table 2. Table 2. Power On Default Settings Operating Mode Part Number
UHF oscillator frequency (MHz) RFOUT power (dBV)(1)
Default Values MC44CC373CA
591.25 89 5.5 31.25 Low 12 On B/G
MC44CC373CAS
591.25 89 5.5 31.25 Low 12 On B/G
MC44CC374CA
591.25 89 5.5 31.25 Low 12 On B/G
MC44CC374T1A
871.25 89 5.5 31.25 Low 12 On B/G
Sound frequency (MHz) Sound reference frequency (kHz) Logic Output Port (logic level) Picture to sound ratio (dB) Peak White Clip (state) System Standards
1. Refer to application note to obtain 82 dBV or other RF levels.
POWER ON RESET A power-on reset circuit holds the digital portion in reset until the power supply has stabilized. Additionally a delay of approximately 2 seconds allows the crystal oscillator to stabilize before the digital section begins normal operation. TRANSIENT OUTPUT INHIBIT To minimize the risk of interference to other channels while the UHF PLL is acquiring a lock on the desired frequency, the Sound and Video modulators are turned OFF during a time out period in two cases: Power On and UHF oscillator power On (OSC bit switched from OFF to normal operation). There is a time out of 262 ms until the output is enabled. This lets the UHF PLL settle to its programmed frequency. STANDBY MODES During standby mode, the modulator is switched to low power consumption. The sound oscillator, UHF oscillator, and the video and sound modulator section's bias are internally turned OFF. The I2C bus section remains active. The standby mode is set with a combination of 3 bits: OSC=1, SO=1 and ATT=1 for MC44CC373/374CAxxx OSC=0, SO=1 and ATT=1 for MC44CC374T1Axx Programming of the Frequency Registers or the Optional Control Registers is not allowed in Standby Mode. SYSTEM L OR B/G SELECTION The SYSL enable control bit internally switches the following functions: * SYSL = 0 enables B/G system CRYSTAL REFERENCE OSCILLATOR The reference crystal frequency is 4.0 MHz, the same as for the legacy modulators. The reference crystal oscillator if followed by a fixed divide-by-128, resulting in a reference frequency of 31.25 kHz for the phase detector. UHF PLL SECTION The UHF VCO runs at twice the desired RF frequency and is divided by 2 before it is sent to the divide-by-8 prescaler and then the programmable divider. The programmable divider division-ratio is controlled by the state of control bits N0 to N11 and is the binary number for the number of 250 kHz steps in the desired RFOUT frequency. The divider-ratio N for a desired frequency F (in MHz) is given by: ( 2 x F ) 128 N = ----------------- x --------16 4 with:
N = 2048 x N11 + 1024 x N10 + ...... + 4 x N2 + 2 x N1 + N0
-- Video modulation polarity: Negative -- Sound modulation: FM
* SYSL = 1 enables L system
NOTE: Programming a division-ratio N = 0 is not allowed. Programming of the N value must be performed while the modulator is in normal mode, not standby mode.
-- Video modulation polarity: Positive -- Sound modulation AM
MC44CC373 4 Digital Home Freescale Semiconductor
UHF OSCILLATOR-VHF RANGE For VHF range operation, the UHF oscillator can be internally divided by: 2, 4, 8, or 16. This is accomplished via the special test mode bits, X2:X0. NOTE: The MC44CC373/374 modulators are intended for UHF operation. Using the digital dividers for VHF operation will cause additional spurious content in the RFOUT. Performance specifications for VHF operation are not provided. The user must provide external filtering on RFOUT to meet their VHF spurious requirements. SOUND SECTION The sound oscillator is fully integrated and does not require any external components. An internal low-pass filter and matched structure provide very low harmonics levels. The sound modulator system consists of an FM modulator incorporating the sound subcarrier oscillator. An AM modulator is also included in the MC44CC373/374xxxx devices and is enabled by the SYSL control bit for use in system L applications. The audio input signal is AC-coupled into the amplifier, which then drives the modulators. The sound reference divider is programmed by control bit SRF, resulting in a reference frequency of 31.25 kHz or 62.5 kHz. The sound subcarrier frequency is selected by control bits SFD1:SFD0. The subcarrier frequencies are 4.5, 5.5, 6.0 or 6.5 MHz. The power-up default value is 5.5 MHz. A capacitor is connected to the external pin, PREEM, to set the pre-emphasis time constant for the application. Information on the selection of this filter may be found later in this document under applications information. LOGIC OUTPUT PORT (LOP) The LOP pin controls any logic function. The primary applications for the LOP are to control an external attenuator or an external switch, between the antenna input and TV output. A typical attenuator application with PIN diode is shown in Figure 3. The LOP pin switches the PIN attenuator depending on the signal strength of the Antenna Input. This reduces the risks of intermodulation in certain areas. The LOP can also be used as an OFF position bypass switch or for other logic functions in the application.
VIDEO SECTION - PEAK WHITE CLIP The modulators require the following for proper video functionality: * A composite video input with negative going sync pulses * A nominal video level of < 1.14 V This signal is AC-coupled to the video input where the sync tip level is clamped. The video signal is then passed to a Peak White Clip (PWC) circuit. The PWC circuit function soft-clips the top of the video waveform, if the sync tip amplitude to peak white clip goes too high. This avoids carrier over-modulation by the video. The Peak White Clip level may be set via the Option Control Register 2, bits PW1:PW0. Clipping can be disabled by software via bit PWC in the Control register. TEST PATTERN GENERATOR The modulators have a simple test pattern generator, that may be enabled under I2C bus control, to permit a TV receiver to easily tune to the modulator output. The pattern consists of two white vertical bars on a black background and a 1 kHz audio test signal. The video test pattern consists of two signals generated by the Digital section. One controls the sync pulse circuitry, and the other controls the luminance circuitry. These signals are logic levels that drive the video circuitry which creates a composite signal with the proper levels for sync pulses and luminance as shown in Figure 4.
TE2
7/10
3/10
TE1 0
4.75s
10 20 24 2830 40 44 50 60 64
TIME IN S.
Vcc
Figure 4. Test Pattern Generator
Antenna Input
TV Out
LOP pin
Figure 3. Typical Attenuator Application with Pin Diode
MC44CC373 Digital Home Freescale Semiconductor 5
ELECTRICAL SPECIFICATIONS
Table 3. Absolute Maximum Ratings Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolutemaximum-rated conditions is not implied. Characteristic
Supply Voltage I2C Input Voltage (SCL and SDA pins) Any Other Input Voltage Storage Temperature Range Junction Temperature
Symbol
VCC VINI2C VIN Tstg TJ
Min
-0.3 -0.3 -0.3 -65 --
Max
+3.6 +5.5 VCC + 0.3 +150 +105
Units
V
V C C
Table 4. General Specifications Characteristic
ESD Protection (Charge Device Model) ESD Protection (Human Body Model) Latch-Up Immunity Thermal Resistance from Junction to Ambient 1. JEDEC JESD22-A114D.
(1)
Symbol
CDM HBM LU RJA
Min
500 2000 200 --
Typ
-- -- -- 102
Max
-- -- -- --
Units
V V mA C/W
Table 5. Recommended Operating Conditions Characteristic
Supply Voltage Total supply current (all sections active) Total standby mode supply current Test pattern sync pulse width Sound comparator charge pump current RF comparator charge pump current Logic Output Port Saturation voltage at I OL=2 mA Leakage current Ambient Temperature While locking When locked
Symbol
VCC ICC ICC -- -- -- -- VOL IOH TA
Min
+3.0 65 15 3 1 -- 1.2 -- -- 0
Typ
+3.3 85 22 4.7 3.9 1 1.6 160 -- --
Max
+3.6 98 30 6.5 7 1.5 2 300 1 +70
Units
V mA mA S A A mA mV A C
NOTE: Crystal specification reference information Frequency = 4 MHz Mode = Parallel Resonance Load Capacitance = 27 pF Motional Resistance = 10 Ohms Typical (100 Ohms Maximum Starting)
MC44CC373 6 Digital Home Freescale Semiconductor
PERFORMANCE CHARACTERISTICS
Unless otherwise stated, all performance characteristics are for: * Power Supply, VCC = 3.3 V * Ambient Temperature, TA = 25o C * Video Input 1.0 V(pp) 10-step grayscale. * RF inputs/outputs into 75 load. NOTE: Specifications only valid for envelope demodulation. Table 6. High Frequency Characteristics Parameter
RFOUT output level(2)
The parameters listed are based on the type of test conditions found in the column Type. * A = 100% tested * B = 100% Correlation tested * C = Characterized on samples * D = Design parameter See "Characterization Measurement Conditions" on page 18 for each C type parameter.
Test Conditions(1)
Output signal from modulator section
Device
MC44CC373CA MC44CC374CA MC44CC374T1A
Min
83
Typ
89
Max
93
Unit
dBV
Type
B
UHF oscillator frequency VHF range RFOUT output attenuation UHF oscillator internally divided During transient output inhibit, or when ATT bit is set to 1.
460 45 50 -- -- -- --
-- -- 60 -63 -54 -65 12
880 460 -- -40 -- -- 30
MHz MHz dBc dBc dBc dBc dBV
A B B C C C C
Sound subcarrier harmonics (Fp+nFs) Reference picture carrier. Second harmonic of chroma subcarrier Using red EBU bar. Chroma/Sound intermodulation: Fp+ (Fsnd - Fchr) Out-of-band (UHF picture carrier) spurious (Fo = 460 - 880MHz) Using red EBU bar. 1/4Fo, 1/2Fo, 3/4Fo, 3/2Fo Output measured from 40 MHz to 1 GHz. 2nd harmonic 3rd harmonic No video/sound modulation.
Fo (picture carrier) harmonics(2)(3) In band spurious (Fo @5MHz)
-- -- --
66 69 --
74 78 -65
dBV dBc
C C
1. See Performance Measurement Test Set-ups, Table 9. 2. Refer to application note to obtain 82 dBV or other RF levels and to reduce picture carrier harmonics. 3. Picture carrier harmonics are highly dependent on PCB layout and decoupling capacitors.
MC44CC373 Digital Home Freescale Semiconductor 7
Table 7. Video Performance Characteristics Parameter
Video bandwidth Video input level Video input current Video input impedance Peak White Clip Video S/N Differential Phase Differential Gain Luma/Sync ratio PAL video modulation depth (SYSL = 0) SECAM video modulation depth (SYSL = 1) PWC bit set to 0. CCIR Test Line 310, worst of first 4 out of 5 steps. Input ratio 7.0:3.0 1.0 Volt Peak-to-Peak input. Gain set to default Video Modulation depth for video=1.4 VCVBS at default (01) PWC level No sound modulation,100% white video. Using CCIR Rec.567 weighting filter. 75 load
Test Conditions(1)
Reference 0 dB at 100 kHz, measured at 5 MHz.
Min
-0.5 -- 8 75 90.5 53 +5 -5 6.8/3.2 75 90
Typ
0.1 1.0 10 92 94 55 -- -- -- 83 96
Max
0.5 1.5 12 110 97.5 -- -5 5 7.2/2.8 88 99
Unit
dB VCVBS A K % dB deg % -- % %
Type
C D A A B C C C B B B
1. See Performance Measurement Test Set-ups, Table 22.
Table 8. Audio Performance Characteristics Parameter
Picture-to-Sound ratio Audio modulation index
Test Conditions(1)
PS bit 0 setting Using specific pre-emphasis circuit, audio input level=200 mVrms -audio frequency=1 kHz AM modulation: SECAM Fs=6.5MHz FM modulation: Fs=5.5, 6 or 6.5MHz 100% modulation= 50 kHz FM deviation FM modulation: NTSC Fs=4.5MHz 100% modulation= 25 kHz FM deviation
Min
9
Typ
--
Max
19
Unit
dB
Type
A
76 95 95 60
80 100 100 71 -- -- 0.5 1.5 54
86 104 104 80 +2.0 +2.0 1 2.5 --
% % % K dB dB % % dB
A A A A C
Audio input impedance Audio Frequency response Reference 0dB at 1 kHz, using specified pre-emphasis circuit, measure from 50 Hz to 15 kHz No pre-emphasis. Measure from 50 Hz to 50 kHz At 1 kHz, 100% modulation (50 kHz). Pre-emphasis. No video. At 1 kHz, 100% modulation Pre-emphasis. No video Ref 1 kHz, 50% modulation (25 kHz) EBU color bars Video signal, using CCIR 468.2 weighting filter. Pre-emphasis. Reference 1 kHz, 85% modulation Video input EBU color bar 75% Audio BW 40 Hz - 15 kHz Weighting filter CCIR 468-2. Pre-emphasis. No Pre-emphasis No Pre-emphasis. 50 Hz to 50 kHz BW
-2.5 0.5 -- -- 50
Audio Frequency response Audio Distortion FM (THD only) Audio Distortion AM (THD only) Audio S/N with Sync Buzz FM
C C C C
Audio S/N with Sync Buzz AM
45
50
--
dB
C
Total Harmonic Distortion (THD) Signal-to-Noise Ratio (SNR)
-- 58
-- --
0.1 --
% dB
C C
1. See Performance Measurement Test Set-ups, Table 22.
MC44CC373 8 Digital Home Freescale Semiconductor
HIGH SPEED I2C CONTROL INTERFACE OPERATION
The modulator chip's digital control interface is compatible with the I2C bus standard. The two pins used for the I2C bus are the clock (SCL) and data (SDA). The data pin is bidirectional. The I2C interface lines are 5 Volt tolerant. Therefore, they can be pulled up to 5 Volts, if required, to interface with the microprocessor in a given application. NOTE: If the MC44CC373/4 modulator is powered down, it will load the I2C bus by means of leakage current passing through the stacked ESD protection diodes on the SCL and SDA pins. The input control data stream is clocked in on the rising edge of SCL, with the most significant bit, MSB, first. The seven-bit IC Address and R/W bit are in the first byte sent. This allows the IC to determine if it is the device that is being communicated with. After that, an even number of control data bytes, 8-bits each, sent to configure the IC. The data stored in the input control register is loaded into the appropriate device registers during the acknowledge, ACK, bit time. The Master controls the clock line, whether writing to the part or reading from it. After each byte that is sent, the device that receives it, sends an acknowledge bit back to the master. After the last data byte and ACK, the master sends a Stop Condition to terminate the write cycle. Table 10. Chip Address by Orderable Part Number Orderable Part Number
MC44CC373CA, MC44CC374CA, MC44CC374T1A MC44CC373CAS
Status data can be read back from the modulator chip. The output status data is clocked out on the falling edge of SCL and is valid on the rising edge, with the MSB first. IC Device Address Since the I2C bus is a two-wire bus that does not have a separate chip-select line, each IC on the bus has a unique address. This address must be sent each time an IC is communicated with. The address is the first seven bits that are sent to the IC as shown in Table 9. The eighth bit sent is the R/W bit, it determines whether the master will read from or write to the IC. Table 9. IC Address Byte Format
7 6 5 4 3 2 1 0
IC Address
A6 1 A5 1 A4 0 A3 0 A2 1 A1 X A0 1
Read/ Write
R/W X
Address bit A1 selects one of two possible addresses. The chip address is defined by the orderable part number as listed in Table 10. The RW bit determines if the master is requesting a read or write. RW = 0 = write and RW = 1 = read.
IC Address Byte A1
0 0 1 1
RW
0 1 0 1
Mode
Write Read Write Read
Binary
1100_1010 1100_1011 1100_1110 1100_1111
Hex
0xCA 0xCB 0xCE 0xCF
I2C Write Mode Format In the write mode, each ninth data bit is an acknowledge bit (ACK) as shown in Figure 5. During this time, the Master lets go of the bus, the external pull-up resistor pulls the signal high and sends a logic 1 and the Modulator circuit (slave) answers on the data line by pulling it low. Besides the first byte with the chip address, the circuit needs two or more data bytes for operation. The programming of the MC44CC37xxxxx devices is similar to the legacy devices. That is, they may be programmed with either two or four data bytes, after the chip address. Table 11 shows the permitted data bytes, and the order in which they can be sent, to program the MC44CC373/374 devices. Examples 1 and 2 are the same as the legacy modulators. The control data bytes all contain an address function bit (the MSB) which lets the IC distinguish between the frequency information and control information. If the address function bit is a logic 1, the following bytes contain control information. The frequency information has the address function bit that is
set to a logic 0. This allows the frequency or the control information to be sent first as shown inn Examples 3,and 4. The MC44BS373/4 legacy family of RF modulators required only two words of data (four bytes) for full configuration. The new CMOS devices have two additional (optional) control words that can be used to access some new features. These features include changing the output power, using a different frequency crystal, and adjusting the peak white clip levels. These new Option Control words do not need to be sent unless access to these new features is desired. The default values for these functions will allow the device to work the same way as the MC44BS373/4 devices did. Example 5 shows how the new Option Control words are to be sent. OC1 follows the Control word and OC2 follows OC1. Example 6 shows the Frequency word being sent first followed by the Control bytes.
MC44CC373 Digital Home Freescale Semiconductor 9
The following rules apply for the sequences of data bytes for incoming (write) information: * If an odd number of data bytes are received, the last one is ignored. * If nine data bytes are received, the ninth and following ones are ignored, and the last ACK pulse is sent at the end of the eighth data byte. * The optional control register one, most significant and least significant bytes, OC1M, OC1L, data must
*
*
always be sent after the C1,C0 control data without a stop condition in between. The optional control register two, most significant and least significant bytes, OC2M, OC2L, data must be sent directly after the OC1M, OC1L data without a stop condition in between. The Control and Frequency information may be sent as separate I2C write sequences. (Example 1 or Example 5 followed/preceeded by Example 2).
Table 11. MC44CC373/4 Programming Sequence (Incoming Information) Legacy Devices Data Bytes
Example 1 Example 2 Example 3 Example 4 STA STA STA STA CA CA CA CA C1 FM C1 FM C0 FL C0 FL STO STO FM C1 FL C0 STO STO
MC44CC37xxxxxx Devices using the Option Control Bytes
Example 5 Example 6 STA STA CA CA C1 FM C0 FL OC1M C1 OC1L C0 OC2M OC1M OC2L OC1L STO OC2M OC2L STO
Abbreviations: STA = Start condition CA = Chip Address FM = Frequency information, most significant (high order) bits FL = Frequency information, least significant (low order) bits C1 = Control information, most significant (high order) bits CO = Control information, least significant (low order) bits OC1M = Optional Control 1 information, most significant (high order) bits OC1L= Optional Control 1 information, least significant (low order) bits OC2M = Optional Control 2 information, most significant (high order) bits OC2L = Optional Control 2 information, least significant (low order) bits STO = Stop condition
I2C Read Mode Format To read back the status data, the read address shown in Table 10 is sent by the master. The modulator then responds with an ACK followed by a byte containing status information on the RF oscillator out-of-frequency range.
MC44CC373 10 Digital Home Freescale Semiconductor
I2C BIT MAPPING SUMMARY
WRITE MODE
CA-CHIP ADDRESS FM-High Order Bits FL-Low Order Bits C1-High Order Bits C0-Low Order Bits OC1M-High Order Bits OC1L-Low Order Bits OC2M-High Order Bits OC2L-Low Order Bits
Bit 7
1 0 N5 1 PWC 1 0 1 0
Bit 6
1 TPEN N4 AUX OSC 0 0 0 0
Bit 5
0 N11 N3 SO ATT 0 0 0 0
Bit 4
0 N10 N2 LOP SFD1 0 0 0 0
Bit 3
1 N9 N1 PS SFD0 0 0 0 0
Bit 2
see Table 9 N8 N0 X3 SREF 0 0 0 0
Bit 1
1 N7 X1 X2 X5 0 0 0 PW1
Bit 0
0 N6 X0 SYSL X4 0 0 0 PW0
ACK
ACK ACK ACK ACK ACK ACK ACK ACK ACK
READ MODE
CHIP ADDRESS R-Status Byte
Bit 7
1 --
Bit 6
1 --
Bit 5
0 --
Bit 4
0 --
Bit 3
1 --
Bit 2
see Table 9 Y2
Bit 1
1 Y1
Bit 0
1 OOR
ACK
ACK --
Bit Name
AUX ATT LOP N0...N11 OSC OOR PS PWC SFD0, 1 PW0, PW1 SO SREF SYSL TPEN X5...X0 Y1, Y2 Auxiliary sound input enable/disable.
Description
Modulator output attenuated-sound and video modulators ON/OFF Logic Output Port UHF frequency programming bits, in steps of 250 kHz UHF oscillator ON/OFF RF oscillator out-of-frequency range information Picture-to-sound carrier ratio Peak White Clip enable/disable Sound subcarrier frequency control bits Peak White Clip Level. (see Table 20) Sound Oscillator ON/OFF Sound PLL Reference frequency System L enable-selects AM sound and positive video modulation. (MC44CC373/374xxxx only) Test pattern enable-picture and sound Test mode bits-All bits are 0 for normal operation. (see Table 18) RF oscillator operating range information
MC44CC373 Digital Home Freescale Semiconductor 11
I2C PROGRAMMING SUMMARY TABLES
Sound SFD1
0 0 1 1
UHF SFD0
0 1 0 1
Sound Subcarrier Freq (MHz)
4.5 5.5 6.0 6.5
OSC
UHF Oscillator MC44CC373/ 374CAxxx MC44CC374T1Axx
UHF oscillator disabled. Normal operation.
0 1
Normal operation. UHF oscillator disabled.
PS
0 1
Picture-to-Sound Ratio (dB)
12 16
When UHF oscillator is disabled, do not program the frequency register N; also writing to Option Control Registers 1 and 2 is not allowed. ATT
0 1
Modulator Output Attenuation
Normal operation Modulator output attenuation (sound and video modulators sections bias turned OFF.
SO
0 1
Sound Oscillator
Sound oscillator ON (Normal mode) Sound oscillation disabled (oscillator and PLL section bias turned OFF)
AUX
0 1
Auxiliary Audio Input
AUX input disabled (normal mode) AUX input enabled
Sound PLL SREF
0 1
Description
Sound Reference frequency = 31.25 kHz Sound Reference frequency = 62.5 kHz
Video SYSL System L/BG Selection
SYSL only applies to MC44CC373/374xxxx 0 1 System B/G enabled, System L disabled (FM sound and negative video modulation) System L enabled, System B/G disabled (AM sound and positive video modulation)
Standby Mode OSC
1 0
SO
1 1
ATT
1 1
Combination of 3-bits
Modulator standby mode (MC44CC373/374CAxx) Modulator standby mode (MC44CC374T1Axx)
PWC
0 1
Peak White Clip
Peak White Clip ON (System B/G) Peak White Clip OFF (System L)
Do not program the frequency register N value and Optional Control Registers during standby mode.
PW1
0 0 1 1
PW0
0 1 0 1
Peak White Clip Level
Logic Output Port LOP Description
Pin 3 is low voltage Pin 3 is high impedance
1.0 Volt - Default
0 1
TPEN
0 1
Test Pattern Signal
Test pattern signal OFF (normal operation) Test pattern signal ON (picture and sound)
MC44CC373 12 Digital Home Freescale Semiconductor
INTER-IC (I2C) INTERFACE TIMING
MSB IC Address R/W AD7 AD1 0
Slave Ack
Master Writes to Slave Byte 2 R15 R8
Slave Ack
S SDA
Byte 1 R7 R0
Slave Ack
LSB Additional Control Bytes R15 R8
Slave Ack
P
S
R7 tBUF
SCL tHD;STA Start Condition Sample Input tf tr tHIGH tLOW tSU;DAT tHD;DAT tSU;STO Stop Condition
MSB IC Address R/W S SDA AD7 AD1 1
Slave Ack
Master Reads from Slave Status Byte
LSB P
D7
D6
D5
D4
D3
D2
D1
D0
Master Not Ack
SCL Start Condition tSP Figure 5. I2C Timing Diagram Table 12. I2C Interface Bus Specifications Parameter
Low Level Output Voltage High Level Input Voltage Low Level Input Voltage Absolute Max Input Voltage Hysteresis of Schmitt trigger inputs Capacitance for each I/O pin(1)
Stop Condition
Symbol
VOL VIH VIL -- Vhys CIN tSP fSCLK tHD;STA tSU;STA tSU;DAT tHD;DAT tSU;STO tLOW tHIGH tr tf tBUF
Min.
0 0.7VCC -0.5 -- 0.05VCC -- 0 0 500 500 100 0 500 0.6 0.6 20+ 0.1Cb 20+ 0.1Cb 200
Max.
0.4 VCCmax+0.5 0.3 VCC 5.5 -- 10 50 800 -- -- -- -- -- -- -- 300 300 --
Units
V V V V V pF nS kHz nS nS nS nS nS uS uS nS nS nS
Pulse width of spikes filtered out SCL Frequency Hold time Start condition Set-up time for repeated start Data Set-up time Data Hold time Set-up time for Stop condition Low period of the SCL clock High period of the SCL clock Rise time of both SDA and SCL Fall time of both SDA and SCL Bus free time between Stop and Start 1. Cb = total capacitance of one bus line in pF.
MC44CC373 Digital Home Freescale Semiconductor 13
CONTROL AND DATA REGISTER - DEFINITIONS
The legacy MC44BS373/4 modulators had two 16-bit control registers (Control and Frequency) and one data/status register. The new MC44CC373/374 family has the same register configuration and may be programmed with the same program software as the legacy devices. This backward compatibility allows a faster migration to new product redesigns. There are some additional control features that may be used in new designs. However, it is not necessary to program MSB
R15 1 1 Adr R14 0 AUX R13 0 SO R12 0 LOP R11 0 PS R10 0 X3 R9 0 X2 R8 0 SYSL R7 0 PWC R6 0 OSC R5 0 ATT R4 0 SFD1 R3 1 R2 0 R1 0 X5
these bits when upgrading a legacy system with the new modulator family. CONTROL REGISTER FORMAT The control register format is shown in Figure 6 and the descriptions for the High-order and Low-order bits (bytes) are listed in Table 13 and Table 14 respectively.
LSB
R0 0 X4 Reset State
SFD0 SREF
TEST MODE
TEST MODE
Figure 6. Control Register Format Table 13. Control Register (High-order) Bit Description Bit Name
15 Adr
Table 14. Control Register (Low-order) Bit Description Bit Name Description
Peak White Clip enable/disable 7 PWC 0 1 Peak White Clip on (system B/G). Peak White Clip off (system L).
Description
Address Function bit. Must be set to a logic 1. Gates the AUXIN pin
14
AUX
0 1
Disable AUXIN pin. Enable AUXIN pin.
UHF oscillator On/Off MC44CC373/ MC44CC374T1Axx 374CAxxx 6 OSC 0 1 Normal operation. UHF oscillator disabled.
Sound Oscillator On/Off 13 SO 0 1 Sound oscillator is on (normal mode). Sound oscillator is disabled (osc and PLL section bias is turned off).
Logic Output Port 12 LOP 0 1 LOP pin is low voltage. LOP pin is high impedance. 5 ATT
UHF oscillator Normal operation. disabled.
Modulator output attenuated. 0 1 Normal operation. Modulator output attenuation (sound and video modulator sections bias is turned off).
Picture-to-sound carrier ratio 11 PS 0 1 10 9 X3 X2 Picture-to-sound carrier ratio is 12 dB. Picture-to-sound carrier ratio is 16 dB. 4 SFD1
Sound subcarrier frequency control bits.
Test Mode bits, must be set to logic 0 for normal operation. Test Mode bit. May be used for VHF divider System L Enable - Selects AM sound and positive video modulation. (Applies to MC44CC373xxx devices only. For the MC44CC374xxx devices this bit is set to 0 and may not be modified).
SFD1 SFD0
0 0 0 1 0 1
Frequency
4.5 MHz 5.5 MHz 6.0 MHz 6.5 MHz
3
SFD0
1 1
8
SYSL
0 1
System B/G enabled (FM sound and negative video modulation). System L enabled (AM sound and positive video modulation).
Sound PLL reference frequency 2 SREF 0 1 1 0 X5 X4 Sound reference frequency = 31.25 kHz Sound reference frequency = 62.5 kHz
Test Mode bits, must be set to logic 0 for normal operation.
MC44CC373 14 Digital Home Freescale Semiconductor
FREQUENCY REGISTER FORMAT The format for the frequency register is shown in Figure 7. The descriptions for the High-order and Low-order bits (bytes) are listed in Table 15 and Table 16 respectively. MSB
R15 0 0 Adr R14 0 TPEN Test Ptrn N11 N10 N9 R13 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 0 N2 N1 N0 X1
LSB
R0 0 X0 Reset State
See Table 17 for the default (reset) value. N8 N7 N6 N5 N4 N3
N Counter Figure 7. Frequency Register Format
TEST MODE
Table 15. Frequency Register (High-order) Bit Description Bit Name
15 Adr
Table 16. Frequency Register (Low-order) Bit Description Bit Name
7 6 5 4 3 2 N5 N4 N3 N2 N1 N0 X5 X4 Test Mode bits, must be set to logic 0 for normal operation. May be used for VHF divider. N Counter program bits, N5:N0.
Description
Address Function bit. Must be set to a logic 0. Test Pattern Enable.
Description
14
TPEN
0 1
Test pattern signal off (normal operation). Test pattern signal on (picture and sound).
13 12 11 10 9 8
N11 N10 N9 N8 N7 N6 N Counter program bits, N11:N6.
1 0
The N Counter bits determine what UHF frequency is used. N11:N0 is the binary number of 250 kHz steps in the desired RFOUT frequency F. With:
N = 2048 x N11 + 1024 x N10 + ...... + 4 x N2 + 2 x N1 + N0
NOTE: Programming a division-ratio N = 0 is not allowed. At power up the modulator will assume a default value for the N Counter. The default is determined at time of manufacture and is listed in Table 17 by the orderable part number.
Table 17. Power-On Default Values for N Counter by Orderable Part Number Orderable Part Number
MC44CC373CAEF, MC44CC373CASEF, MC44CC374CAEF MC44CC374T1AEF
Frequency
591.25 871.25
N Counter Value Decimal
2365 3485
Hex
0x93D 0xD9D
Binary
1001 0011 1101 1101 1001 1101
MC44CC373 Digital Home Freescale Semiconductor 15
The Test Mode bits, X5:X0, found in the frequency and control registers, control 15 different test mode states. Only four of these states have an application use. All other states are intended for manufacturing test purposes only. The test mode states defined by X2:X0 in Table 18 may be used to operate the modulator in the in VHF range. Table 18. Test Modes usable for VHF operation X5
0 0 0 0 0 x
It should be noted that operation in the VHF range has a high spurious content due to the digital dividers. Filtering of the RFOUT signal may be required to meet desired performance specifications. Performance data is not provided for VHF operation.
X4
0 0 0 0 0 x
X3
0 0 0 0 0 x
X2
0 0 0 0 1 1
X1
0 0 1 1 0 x
X0
0 1 0 1 0 x
Description
Normal Operation RF/2 RF4 RF/8 RF/16 The 11 other test mode states are reserved for manufacturing test purposes.
OPTION CONTROL REGISTER 1 FORMAT The format for the Optional Control Register 1, OCR1, is shown in Figure 8. Bits R14:R0 are not defined for system applications. They are for manufacturing test only. For normal operation these bits must be set to a logic 0. When MSB
R15 1 1 Adr R14 0 R13 0 R12 0 R11 0 R10 0 R9 0 R8 0 R7 0
UHF oscillator is disabled, do not write to Option Control Register 1 and 2. Any other time, writing to Option Control Registers 1 and 2 is allowed.
LSB
R6 0 R5 0 R4 0 R3 0 R2 0 R1 0 R0 0 Reset State
Reserved for manufacturing test purposes only
Reserved for manufacturing test purposes only
Figure 8. Option Control Register 1 Format
Table 19. Option Control Register 1, Bit Description Bit
15 14-8 7-0
Name
Adr -- --
Description
Address Function bit. Must be set to a logic 1. Reserved for manufacturing test. Reserved for manufacturing test.
MC44CC373 16 Digital Home Freescale Semiconductor
OPTION CONTROL REGISTER 2 FORMAT The format for the Optional Control Register 2, OCR2, is shown in Figure 9. Bits R14:R2 are not defined for system MSB
R15 1 1 Adr R14 0 R13 0 R12 0 R11 0 R10 0 R9 0 R8 0 R7 0
applications. They are for manufacturing test only. For normal operation these bits must be set as defined by the reset state. LSB
R6 0 R5 0 R4 0 R3 0 R2 1 R1 0 PW1 R0 1 PW0 Reset State
Reserved for manufacturing test purposes only
Peak White clip level
Figure 9. Option Control Register 2 Format
The Peak White Clip level may be set by setting bit PW1 and PW0 as listed in Table 20. The default (power-up) setting is 1.0 volts. When UHF oscillator is disabled, do not write to Option Control Registers 1 and 2. Any other time, writing to Option Control Registers 1 and 2 is allowed.
Table 20. Option Control Register 2, Bit Description Bit Name
15 14-2 Adr --
Description
Address Function bit. Must be set to a logic 1. Reserved for manufacturing test. Peak White Clip level
1
PW1
PW1 0 0
PW0 0 1 0 1
Video Modulation Depth for video = 1.4 VCVBS 90% 94% 91% 92.5%
0
PW0
1 1
DATA/STATUS REGISTER FORMAT The data/status read back format is shown in Figure 10. The first byte contains the status information on the RF oscillator out-of-frequency range and is the same format used by the legacy devices. Therefore, current legacy software will be unaffected as it will only read back this most significant byte. During manufacturing test, additional two byte registers are read back without sending a stop condition. This read back data has no significance to end system applications. Therefore if it is read by a master, it should be ignored. The bit description for the status byte is listed in Table 21.
Table 21. Status Byte Bit Description Bit
R7:R3
Name
Reserved
Description
Frequency Too High / Too Low 0
R2
Y1 1
VCO out of range, frequency too low, only valid if OOR=1 VCO out of range, frequency too high, only valid if OOR=1
Low/High VCO Active R1 Y2 0 1 High VCO is active Low VCO is active
MSB
R7 R6 R5 Reserved R4 R3 R2 Y2 R1 Y1 OSC Status
LSB
R0 OOR R0 OOR
UHF Osc Out of Freq. Range 0 1 Normal operation, VCO in range VCO out of range
Figure 10. Status/Data Register Format
MC44CC373 Digital Home Freescale Semiconductor 17
CHARACTERIZATION MEASUREMENT CONDITIONS
The default configuration unless otherwise specified: * Peak White Clip enabled * UHF oscillator ON * Sound and video modulators ON * Sound subcarrier frequency = 5.5 MHz * Sound Oscillator ON * Sound PLL reference frequency = 31.25 kHz * Logic Output Port LOW Table 22. Performance Measurement Test Set-ups Device and Signals Set-up RFOUT Output Level Video: 10 steps grey scale No audio Measured picture carrier in dBV with a Spectrum Analyzer using a 75 to 50 transformation, all cables losses and transformation pads having been calibrated. Measurement used as a reference for other tests: RFout_Ref RFOUT Output Attenuation ATT bit = 1 No Video signal No Audio signal Sound Subcarrier Harmonics Video: 10 steps grey scale No Audio signal Measure in dBc second and third sound harmonics levels in reference to picture carrier (RFout_Ref).
Picture carrier Sound carrier
* * * * * * * *
Picture-to-sound carrier ratio = 12 dB System L disabled Test pattern disabled All test mode bits are `0' Frequency from channel 21 to 69 RF Inputs / Output into 75 Load using a 75 to 50 transformation. Video Input 1Vpp. Audio pre-emphasis circuit enabled.
Measurement Set-up
Measure in dBc picture carrier at ATT=1 with reference to picture carrier at ATT=0
Sound 2nd harm Sound 3rd harm Fo +5.5MHz +11MHz +16.5MHz
Second Harmonics of Chroma Subcarrier No audio Video: a 700m V(PP) 4.43 MHz sinusoidal signal is inserted on the black level of active video area. Measure in dBc, in reference to picture carrier (RFout_Ref), second harmonic of chroma at channel frequency plus 2 times chroma frequency, resulting in the following spectrum.
Picture carrier Chroma carrier Frequency 4.43 MHz 700 mVpp Sound carrier Chroma 2nd Harmonic
Fo
+4.43MHz +5.5MHz
+8.86MHz
MC44CC373 18 Digital Home Freescale Semiconductor
Table 22. Performance Measurement Test Set-ups (continued) Device and Signals Set-up Measurement Set-up Chroma/Sound Intermodulation No audio signal Video: 700 mV(PP) 4.43 MHz sinusoidal signal inserted on the black level of active video area.This is generated using a Video Generator and inserting the required frequency from a RF Signal generator. Measure in dBc, in reference to picture carrier (RFout_Ref), intermodulation product at channel frequency plus the sound carrier frequency (+5.5 MHz) minus the chroma frequency (-4.43 MHz), resulting in the following spectrum. Intermodulation product is at the channel frequency +1.07 MHz.
Picture carrier Chroma carrier Frequency 4.43 MHz 700 mVpp Chroma/Sound Intermod. Sound carrier
Fo
+1.07MHz
+4.43MHz +5.5MHz
Picture Carrier Harmonics No Video signal No Audio signal Measure in dBc, in reference to picture carrier (RFout_Ref), second and third harmonic of channel frequency, resulting in the following spectrum.
Picture carrier
2nd harmonic
3rd harmonic
Fo
2Fo
3Fo
Out of Band Spurious No Video signal No Audio signal Measure in dBV spurious levels at 0.25, 0.5, 0.75 and 1.5 times channel frequency, resulting in the following spectrum Measure from 40 MHz to 1 GHz (Fo = 460 - 880 MHz).
Picture carrier
Spurious
Fo/4
Fo/2 Fo*3/4
Fo
Fo*3/2
MC44CC373 Digital Home Freescale Semiconductor 19
Table 22. Performance Measurement Test Set-ups (continued) Device and Signals Set-up In Band Spurious No Video signal No Audio signal Measure in dBc, in reference to picture carrier (RFout_Ref), spurious levels falling into video bandwidth starting from 100 kHz from the picture carrier up to 5 MHz. Video Bandwidth No audio Video: 600m V(PP) sinusoidal signal inserted on the black level of active video area. The Video signal is demodulated on the spectrum analyzer, and the peak level of the 100 kHz signal is measured as a reference. The frequency is then swept from 100 kHz to 5 MHz, and then the difference in dB from the 100 kHz reference level is measured. Weighted Video Signal to Noise Video: 100% White video signal - 1 V(PP). No Audio signal This is measured using a Demodulator in B/G (using a CCIR Rec. 567 weighting network, 100 kHz to 5 MHz band with sound trap and envelope detection, and a Video Analyzer. The Video Analyzer measures the ratio between the amplitude of the active area of the video signal (700mV) and the noise level in Vrms on a video black level which is show below. Video S/N is calculated as 20 x log(700 /N) in dB. Measurement Set-up
N noise level in Vrms
Unweighted Video Signal to Noise Same as above with CCIR filter disabled. Same as above. Video Differential Phase Video: 5 step Grey Scale- 1 V(PP). No Audio signal This is measured using a Demodulator in B/G (using a CCIR Rec. 567 weighting network, 100 kHz to 5 MHz band with sound trap, and envelope detection, and a Analyzer. On line CCIR 330, the video analyzer DP measure consists of calculating the difference of the Chroma phase at the black level and the different chroma subcarrier phase angles at each step of the greyscale. The largest positive or negative difference indicates the distortion.
DIFF PHASE =
the largest positive or negative difference the phase at position 0
* 100%
The video analyzer method takes the worst step from the first 4 steps.
MC44CC373 20 Digital Home Freescale Semiconductor
Table 22. Performance Measurement Test Set-ups (continued) Device and Signals Set-up Video Differential Gain Video: 5 step Grey Scale- 1 V(PP). No Audio signal This is measured using a Demodulator in B/G (using a CCIR Rec. 567 weighting network, 100 kHz to 5 MHz band with sound trap and envelope detection, and a Video Analyzer. On line CCIR 330 shown below, the video analyzer DG measure consists of calculating the difference of the Chroma amplitude at the black level and the different amplitudes at each step of the greyscale. The largest positive or negative difference indicates the distortion. Measurement Set-up
012345
5-step greyscale with Chroma, line CCIR330
the largest positive or negative difference the amplitude at position 0
DIFF GAIN =
* 100%
The video analyzer method takes the worst step from the first 4 steps. Video Modulation Depth No Audio signal Video: 10 step grey scale This is measured using a Spectrum Analyzer with a TV Trigger option, allowing demodulation and triggering on any specified TV Line. The analyzer is centred on the maximum peak of the Video signal and reduced to zero Hertz span in Linear mode to demodulate the Video carrier.
A (mV)
B (mV)
TV Line Demodulated by Spectrum Analyzer-BG standard
The Modulation Depth is calculated as (A - B) / A x 100 in % Same measurement method for L standard, with inverted video. Picture to Sound ratio No Video signal No Audio Signal PS bit set to 0 and 1
Picture carrier
Measure in dBc sound carrier in reference to picture carrier (RFout_Ref) for PS bit = 0 (PS = 12 dB typical) and for PS bit = 1 (PS = 16dB).
Sound carrier
Fo
+5.5Mhz
MC44CC373 Digital Home Freescale Semiconductor 21
Table 22. Performance Measurement Test Set-ups (continued) Device and Signals Set-up Measurement Set-up Audio Modulation Index - FM Modulation Video: Black Sync Audio signal: 1 kHz, 205 mVrms. This is measured using a Demodulator in B/G and an Audio Analyzer at 1 kHz The audio signal 205 mV at 1 kHz is supplied by the Audio Analyzer, and the FM demodulated signal deviation is indicated on the Demodulator in kHz peak. This value is then converted in % of FM deviation, based on specified standards. Audio Frequency Response Video: Black Sync Audio signal: 50 Hz to 15 kHz, 100 mVrms This is measured using a Demodulator in B/G and an Audio Analyzer. The audio signal 1 kHz 100 mVrms is supplied by the Audio Analyzer, demodulated by the Demodulator and the audio analyzer measures the AC amplitude of this demodulated audio signal: this value is taken as a reference (0 dB). The audio signal is then swept from 50 Hz to 15 kHz, and demodulated AC amplitude is measured in dB relative to the 1 kHz reference. Audio pre-emphasis and de-emphasis circuits are engaged, all audio analyzer filters are switched OFF. Audio Distortion FM Audio: 1 kHz, adjustable level Video: Black Sync This is measured using a UHF Demodulator in B/G and an Audio Analyzer at 1 kHz. The output level of the audio analyzer is varied to obtain a deviation of 50 kHz indicated on the Demodulator. The input arms detector of the Audio Analyzer converts the ac level of the combined signal + noise + distortion to dc. It then removes the fundamental signal (1 kHz) after having measured the frequency. The output rms detector converts the residual noise + distortion to dc. The dc voltmeter measures both dc signals and calculates the ratio in% of the two signals. ADist = ( Distortion + Noise ) ( Distortion + Noise + Signal ) Audio Signal to Noise Audio: 1 kHz, adjustable level Video: EBU Color Bars This is measured using a Demodulator in B/G and an Audio Analyzer at 1 kHz. The output level of the Audio analyzer is varied to obtain a Modulation Deviation of 25 kHz indicated on the Demodulator. The Audio Analyzer alternately turns ON and OFF its internal audio source to make a measure of the Audio signal plus noise and then another measure of only the noise. The measurement is made using the internal CCIR468-2 Filter of the Audio Analyzer together with the internal 30 +/-2 kHz (60 dB/decade) Lowpass filters. The demodulator uses a quasi-parallel demodulation as is the case in a normal TV set. In this mode the Nyquist filter is bypassed and the video carrier is used without added delay to effectuate intercarrier conversion. In this mode the phase noise information fully cancels out and the true S/N can be measured. ASN ( dB ) = 20 x log ( Signal + Noise ) ( Noise )
MC44CC373 22 Digital Home Freescale Semiconductor
PIN CIRCUIT SCHEMATICS
VCC VCC
VCC
Pin 8: VIDEOIN Pin 1: SDA
500 10K
10K
VCC
VCC VCC 8K
75
75
Pin 11: RF Output
Pin 3: LOP
8K
VCC
Pin 4: XTAL
Pin 14: PLLFLT
VCC VCC
Pin 15: AUXIN Pin 5: PREM
10k 11.8k
audio
VCC VCC
VCC
50k
Pin 16: SCL
Pin 6: AUDIOIN
VCC
Pin 7: SPLLFLT
Figure 11. Pin Circuit Schematics MC44CC373 Digital Home Freescale Semiconductor 23
2
24
4 3 2 1
5
3.3V R15 0 - DNI R16 0 All Resistors are 5% unless otherwise noted. All Capacitors are XR7/XR5 type unless noted, (10% type are COG/NPO)
MC44CC373
5V R10 10K I2C Control Interface C17 100nF U1 MC44CC373xx / '374xx 1 SDA Note 2 TP1 2 GND C12 33nF R2 7K LOP XTAL PREEMP AUDIO C27 R7 500K C6 2.2uF Note 7 for Stereo R1 L1 8.2uH_c_1008 / 0 ohm R13 220 / 0 ohm R3 75 R14 2.2K / DNI C9 100nF J1 3 2 1 3 2 1 C25 10uF C24 10uF 3.3V R12 ? C11 100nF F1 tps4_5mb2 / DNI 3 1 1.6K 3.3V Note 3 C23 100nF C22 1nF 5V 3.3V R11 ? 5V
B
5V R9 10K Note 5a R8 10K
J2
D
AUX Aurial Input J6
D
TP2 TP3 Logic Output Port AUXIN PLLFLT NC VCC RFOUT GND VCC 9 C14 4.7pF 10 1nF 68nF 8 VIDEO L2 6.8nH C15 6.2pF 11 12 Pin 13 Needs to be Quiet 3.3V 13 14 15 C2 12pF Y1 4.000Mz C1 27pF Note 1 4 5 6 Note 5 Note 3a R6 500K 7 SPLFLT C10 100nF C7 R4 10K 3.3V C5 100nF C4 750pF 5-10% Notes 4,6 C3 1nF C8 100nF C18 1.5pF L3 6.8nH C16 4.7pF C19 1.5pF R18 25 3 SDA SCL 16 C13 4.7nF R5 100K
1 6 2 7 3 8 4 9 5 SCL
DB9_MALE
RF Output J5
C
Audio Input
C
J3
R19 25
R17 100
Video Input
TP4
J4
Resistor Divider for Psudo 3.3V supply
EVALUATION BOARD SCHEMATIC
Figure 12. Evaluation Board Schematic
MTHOLE MT3 MTHOLE
4 3
B
A
Note 8 L1 and F1 are for 4.5MHz NTSC NOTES Audio Traps. Other Video 1. C1 and C2 values depends on the crystal characteristics standards will require use of a Set C2 value such that crystal operates at 4.0MHz. different trap network. C1 = 27pF, C2 = 12pF on the Freescale evaluation board with an ECS Inc. ECS-40-20-1 crystal. 2. RF PLL loop-filter components (C12, C13, R2) must be as close as possible to pin 14 and Ground. J7 J8 3. Supply voltage decoupling capacitors (C3, C8, C22, C23) must be as close as possible to the device power pins (P9, and P12). Power should feed through the caps to the device. J9 3a. Pin 7 bias, connect to pin 9 Vcc. 4. C4 pre-emphasis cap value depends on video standard. PAL B,G,I has a 50S time constant, C4 = 470pF. J10 NTSC M/N has a 75 S time constant, C4 = 750 pF. 5. The value of the audio input capacitor, C5, can be increased to 220nF to improve low frequency response. MT1 MT2 5a. Pull Up resistors R8, R9 required if not on another part of the I2C bus. MTHOLE MT4 Size A MTHOLE Date:
A
STEREO APPLICATIONS ONLY: 6. If the audio signal is encoded and pre-emphasis is applied in the baseband stereo encoder, it is not necessary to add pre-emphasis in the RF modulator and the pre-emphasis capacitor C4 should be removed. 7. Parts as listed are for Mono applications; For Stereo, C6 = 20uF, R1 = 0 ohm, C7 = DNI 8. Audio Trap is to keep wideband video out of the Audio Spectrum. NTSC Part Number = Murata TPSRA4M50B00-B0, PAL Part Number = Murata TPSRA5M50B00.
Title MC44CC373 / '374 CMOS Modulator Schematic Friday, September 12, 2008
2
Rev 0.2 Sheet 1
1
of
1
Digital Home Freescale Semiconductor
5
PACKAGE DIMENSIONS
Figure 13. SOIC-16 Package Dimensions
MC44CC373 25 Digital Home Freescale Semiconductor
Figure 14. SOIC-16 Package Dimensions - continued
MC44CC373 Digital Home Freescale Semiconductor 26
PRODUCT DOCUMENTATION
Refer to the following documents to aid your design process. Application Notes * To be updated.
MC44CC373 27 Digital Home Freescale Semiconductor
How to Reach Us:
Home Page: www.freescale.com Web Support: http://www.freescale.com/support USA/Europe or Locations Not Listed: Freescale Semiconductor, Inc. Technical Information Center, EL516 2100 East Elliot Road Tempe, Arizona 85284 1-800-521-6274 or +1-480-768-2130 www.freescale.com/support Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) www.freescale.com/support Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku, Tokyo 153-0064 Japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor China Ltd. Exchange Building 23F No. 118 Jianguo Road Chaoyang District Beijing 100022 China +86 10 5879 8000 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 1-800-441-2447 or +1-303-675-2140 Fax: +1-303-675-2150 LDCForFreescaleSemiconductor@hibbertgroup.com
Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters that may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals", must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. FreescaleTM and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. (c) Freescale Semiconductor, Inc. 2009. All rights reserved.
RoHS-compliant and/or Pb-free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb-free counterparts. For further information, see http:/www.freescale.com or contact your Freescale sales representative. For information on Freescale's Environmental Products program, go to http://www.freescale.com/epp.
MC44CC373 Rev 3.2 04/2009

▲Up To Search▲

Price & Availability of MC44CC374T1A

	To Download MC44CC374T1A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .